A multi-node-upset-resilient 14T SRAM with high read stability for space applications

Soft error poses reliability challenges in nanometer semiconductor memories. Soft errors in Static Random Access memories (SRAM) occur due to high energy particle's strike on sensitive nodes. This paper presents a new symmetric SRAM cell that enhances the soft error resilience by increasing the cell's critical charge, Qcrit. The proposed cell also removes the read failure problem during read operation. The simulation results carried out using HSPICE confirms that the proposed cell has highest Qcrit. among all other considered cells, which implies that it is least vulnerable to soft-errors. The proposed cell shows 149% and 43% increase in the Qcrit. as compared to the standard 6T and previous hardened cells at VDD=0.5V. The Monte-Carlo simulations for read stability show that the proposed cell exhibits nearly three-fold increase in the read-yield as compared to 6T and previous hardened cells. Therefore, the proposed cell could be a good circuit level solution to enhance the soft error tolerance of memories for space applications where high read stability is equally important.

Background/Objectives: There is an enhancement in the short channel effects and leakage current as the devices are scaled down. Hence, it is almost impossible to design SRAM with high storage capacity and lower power dissipation using the current technology. To achieve higher efficiency and to decrease the power dissipation, a migration to Carbon Nanotube Field Effect Transistor (CNTFET) technology is imperative. GDI technique is one of the low-power methodologies employed to enhance the efficiency of the logic circuit. But to further reduce the leakage power of the circuits, the modified GDI (m-GDI) technique is used. Methods/Statistical analysis: The proposed work aims at designing an 8-T SRAM cell for high read stability and low power dissipation, using the modified GDI cell (m-GDI) technique based on conventional GDI cell. The simulation is done using Cadence Virtuoso with a supply voltage of 900 mV. Stability analysis is also performed for the SRAM cell. Findings: m-GDI technique solves the problem of voltage degradation in GDI technique. An 8-T SRAM cell with low power and high read stability is implemented. CNTs with chirality vector (13, 0) are found to be a good choice for low-power and stable SRAM cell. Improvements/Applications: CNTFET with m-GDI-based memories with their low power and high read stability has the potential to replace the current technology, if the shortcomings in the implementation are conquered.

In this paper, a 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is proposed. In conventional six transistor (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Existing 9T SRAM cell design increases the read static noise margin (SNM) by twice as compared to conventional 6T SRAM cell by completely isolating the bit-lines during the read operation. But the write operation is performed in this cell, by charging/discharging of large bit line capacitances causing 22.5% increase in dynamic power consumption. In the proposed technique, the SRAM cell utilizes charging/discharging of a single bit-line (BL) during write operation, resulting in reduction of dynamic power consumption by 45% as compared to a conventional 6T SRAM cell while the read SNM is also maintained at twice the read SNM of the conventional 6T SRAM cell. All simulations of the proposed 9T SRAM cellhas been carried out in 0.13 ¹m CMOS technology.

Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2times as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.

This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules. Also, the proposed cells uses a single bit-line for both read and write purposes. The cell proposed in this paper consumes less dynamic power and has higher read stability than the standard one. In conventional six-transistor (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. In existing SRAM topologies of 8T, 9T and higher transistor count, the read static noise margin (SNM) is increased but size of the cell and power consumption increases relatively. In the proposed technique, the SRAM cell operates by charging/discharging of a single bit-line (BL) during read and write operation, resulting in reduction of dynamic power consumption to only 40% to 60% (best case/worst case) of that of a conventional 6T SRAM cell. The power consumption is further decreased if the switching operational voltage of the bit-line lies between 0.25VDD to 0.5VDD. All simulations are done using 0.18um Technology.

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct coupling of data storage nodes to the bit lines during a read operation. Lowering of supply and threshold voltages leads to a significant degradation in SRAM cell stability with the scaling of CMOS technology. The SRAM cell stability is further degraded due to the process parameter variations in deeply scaled CMOS technologies. In addition to the data stability issues, the increasing leakage energy consumption of on-chip caches is another growing concern. In this paper, a new nine transistor (9T) SRAM cell with enhanced read stability and reduced leakage power consumption is proposed.

This paper proposes a FinFET-based SRAM cell with data-aware power-gating write-assist to achieve both high read stability and write ability by using read-decoupled access transistors and power-gating PMOSs, respectively, for near-threshold operation. By adaptively cutting off the power-gating PMOS depending on the written data, the write disturbance from power supply can be eliminated, which facilitates more reliable write operation without any additional write assist circuit. Bit-interleaving scheme can be implemented in the proposed SRAM for soft error immunity while ensuring sufficient hold stability in half-selected cells during write operation. The proposed SRAM achieves read stability yield of 8.4σ and write ability yield of 6.1σ and consumes 0.47 pJ energy per operation at supply voltage of 0.4 V, a near-threshold voltage, in a 22-nm FinFET technology.

An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network

Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for near-threshold operation is proposed. In previous local bit-line sharing SRAMs, such as average-8T and full-swing local bit-line (FSLB) SRAMs, multiple bit-cells share a local bit-line pair with a small capacitance for high read stability. However, the average-8T SRAM has a considerably large delay because the full development of the local bit-line cannot be achieved. On the other hand, the FSLB SRAM reduces the delay but requires a timing constraint of control signals to achieve sufficient read sensing margin. The proposed PCLBS SRAM achieves high read speed by fully developing local bit-line pair without a timing constraint. Furthermore, the proposed PCLBS SRAM enhances the read stability and the write ability by, respectively, applying a pre-charged local bit-line scheme and transmission gates in write paths. Based on a 22-nm FinFET technology, the FSLB and proposed PCLBS SRAM have the minimum operating voltages of 0.44 and 0.4 V, respectively, while achieving the $5\sigma$ target read stability and write ability yields. Compared with the FSLB SRAM, the proposed PCLBS SRAM consumes 21% less energy at each minimum operating voltage and has 57% smaller read delay at the operating voltage of 0.4 V.

We have been developing a triple-layer rewritable disc on the base of Blu-ray disc systems using a Mn–Sb–Te–Ge phase-change material and N/2 write strategy. The remarkable features of the Mn–Sb–Te–Ge phase-change material are the high crystallization speed and high thermal stability of amorphous marks. The N/2 write strategy can be set at a long cooling pulse period and can realize the formation of amorphous marks of sufficient size. As a result, a sufficient symbol error rate (SER) and a high read stability were achieved and we confirmed the feasibility of a triple-layer rewritable disc with 100 Gbyte and 72 Mbps recording rate.

This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-trigger inverter write assist technique that controls the trip voltage of the Schmitt-trigger inverter. The proposed Schmitt-trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology.

Physical limitations in scaling of Non-Volatile Memories (NVMs) necessitates alternative ways to increase on-chip storage density and reduce cost. New technologies like MRAMs and PCM, offer advantages in terms of speed and can enable replacement of embedded volatile RAMs with NVMs. Further, storing multiple bits in NVM enables reduction in cost-per-bit. In this work, we propose a four-level sense amplifier (SA) targeted for use in multi-bit resistive NVMs. The proposed, parallel-sensing, multi-level SA has better offset tolerance, double sensing margin, strong positive feedback, and high read stability. Implementation in 65nm LSTP technology achieves 25% faster sensing time (tSEN) than state-of-the-art parallel-sensing design while consuming 28% lesser power at a nominal supply voltage (VDD) of 1.0 V. The proposed design is also 20% denser than the state-of-the-art serial-sensing scheme.

Radiations in space are very critical and may cause failure in the SRAM. Various state-of-the-art SRAMs, such as DICE, Quatro-10T, etc., are proposed to mitigate the failure of SRAM. However, the designs are still vulnerable to radiations causing soft errors. This work proposes a Gate Boosted Radiation Hardened Quadruple 14T SRAM with better Single Node Upset (SNU) and Double Node Upset (DNU) tolerance. It has very high read stability. On top of that, our proposed design outperforms in terms of RSNM, Read Access Time(RAT), Wordline Write Trip Voltage (WWTV), Write Access Time (WAT), and leakage power than most conventional designs. It has a maximum of 1.3x less RAT than SAR-14T, 2.63x more WWTV than Quatro-10T, 1.38× less WAT than Quatro-10T SRAM, and 1.32x less leakage power than SEA-14T SRAM respectively at VDD=0.9V, CMOS 28nm Technology.