A millimeter‐wave scalable small signal model of RF CMOS transistor against number of fingers

Abstract

AbstractA scalable small signal model for RF CMOS transistor is presented in this paper. The model consists of interconnects, substrate network, and intrinsic parameters. The proposed scaling rules characterize the transistors with different numbers of fingers. Based on this, the bias dependency, linear, and nonlinear behavior of all parasitic components are evaluated. A set of scalable RF CMOS models are validated by fabricating in the 90‐nm CMOS process, with gate width of 650 × 8 nm, 650 × 16 nm, 650 × 32 nm, and 650 × 64 nm, respectively. Further, the validity of the proposed model is carried out by comparing the calculated and measured results under different bias conditions up to 66 GHz. The root mean square errors calculated between measured and calculated results are within 0.0110 for S11, 0.0036 for S12, 0.0388 for S21, and 0.0106 for S22, respectively. A fairly good agreement predicts that the model is simple, scalable, and conducive for millimeter‐wave circuits.