Abstract
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.
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