Abstract
Design of a sub-1V supply, half bandgap voltage reference (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> ) is proposed, which can generate V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> of about 620mV and operate with power supply voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> ) as low as about 750mV at 0°C. To enhance manufacturability and facilitate ease of design portability across different process nodes, the design is implemented in standard 180nm digital CMOS without the need for any special CMOS processes or non-conventional devices. The proposed topology only utilizes parasitic substrate bipolar junction transistors (BJT), poly resistors, and normally configured CMOS transistors that chiefly operate in subthreshold. Lower V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> is achieved by segregating BJTs from the resistors used in the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) signal loops. Such configuration results in lowering the emitter-base voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EB</inf> ) via biasing the BJTs at n-times (i.e. 100s of times) lower currents than the PTAT and CTAT resistors and signal loops. Therefore, the scarce V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> headroom in sub-1V applications is freed-up in the PTAT loop from V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EB</inf> by V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> × ln (n), or in the range of typically 10%–15% of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> . Moreover, biasing the BJT loop at nano-ampere currents keeps the power consumption low, while it avoids using prohibitively large PTAT or CTAT resistors.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
