A low power area efficient 10-bit SAR ADC with parasitic insensitive capacitive DAC

Abstract

The designed low power 10-bit 5-MS/s SAR ADC reduces the capacitor array area and switching power by 50% and 89% respectively compared to the conventional one by switching monotonically. The Capacitive digital-to-analog converter used by this ADC diminishes parasitic capacitance as special care has been taken for capacitor array formation. MOM capacitor arrays are done using common centroid placement method and routing matching, in order to achieve low parasitic capacitance, high density and low powered binary weighted capacitor array. A unit MOM capacitor layout structure is done such that it supports placement routing and routing-parasitic matching. The design is implemented in 55nm LPe standard CMOS technology. The implemented ADC was able to achieve SFDR of 74.988 dB, SNDR of 59.831 dB and ENOB of 9.757 bits which consumes 0.627 mW. The active area consumed by the design is only 155×195 μm2.