A Low Power Architecture based on Unidirectional Cut

Abstract

Test power of a circuit mainly consists of capture power and shift power. In this paper, a new scan architecture is proposed to reduce both of them. In the architecture, a new graph algorithm is proposed to partition the scan flip-flops into two parts and then the ones with common successors in each part are grouped as a chain. By partitioning the scan flip-flops into two parts, the process of capture is cut into two sequential steps. This technique can effectively reduce the capture power. Using the clock disabling scheme, we can make sure that, only one or a small portion of scan chains are active during the shifting phase. Therefore, the peak power and average power are reduced. This architecture can effectively reduce the test time too. Experimental result shows that average power and peak power reduction are very significant, compared with the ordinary full-scan architecture.