Abstract
This paper proposes a splitter based parallel multiplier (SBPM) for both signed and unsigned numbers. The proposed SBPM reduces the number of partial products by a factor of two and demands lesser computational complexity compared to Booth multiplier. The synthesis report shows that SBPM is efficient when compared to Booth multiplier in terms of hardware requirements including number of multiplexers, Ex-OR operations, slices and 4 inputs look up table. Simulation result for 8 × 8 SBPM shows that the critical path delay is about 83.5 % of that of Booth multiplier for unsigned numbers and about 72.71 % for signed numbers.
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Schedule a callMore From: Proceedings of the National Academy of Sciences, India Section A: Physical Sciences
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