A layer-based layout approach for semiconductor fabrication facilities

Abstract

Most current semiconductor manufacturing fabrication facilities and those being designed for the future use a bay or process layout configuration. In this approach, the facilities are divided into a number of bays that contain processing equipment. This process layout creates a large amount of material flows between bays. While there may be other, perhaps more efficient layout arrangement strategies, the semiconductor industry is reluctant to adopt these strategies since the bay configuration offers many advantages in terms of maintenance and operation of the physical equipment. In the near future, however, the layout problem of a 300 mm semiconductor wafer fab may pay more attention to material handling than to these advantages due to 300 mm wafer size, weight, and cost issues. The effect on cycle time and WIP level of wafer must be considered especially for the layout of a 300 mm wafer fab. Adopting the idea of group technology (GT) layout, this paper proposes a layer-based approach for solving the fab facility layout problem. This approach groups the equipment of continuous process layers in the same area or cell. The continuous layer groups consist of processing layers with their process steps in sequence. The cell configuration is sequentially determined by the major process flows, and the arrangement of the machines within each cell is a flow-line layout such that the whole process steps of a layer can be done within a cell. An evaluation for layer-based layout in a sample manufacturing environment is demonstrated. Results show the efficiency and effectiveness of the layer-based layout approach.