Abstract
The authors describe a three-valued content-addressable memory cell using a Josephson complementary ternary logic (JCTL) circuit. The memory cell can perform the operations of searching, writing and reading in the ternary logic system. The principle of the memory circuit is illustrated in detail by using the threshold characteristics of the JCTL. Computer simulations were performed to investigate how high-performance operation can be achieved. Simulation results show that the cycle time of memory operation is 120 ps, power consumption is about 0.5 mu W/cell, and tolerances of writing and reading operation are +or-15% and +or-24% respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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