A Highly Flexible Architecture for Morphological Gradient Processing Implemented on FPGA

Abstract

Nowadays, image processing algorithms present essential components of advanced systems in industrial, robotic and medical applications. In most cases, there are high requirements for reduced delays and optimal processing performances. Mathematical morphological operations are one of the most popular and powerful tools used in image processing offering high-level performance operations at low design complexity. However, mathematical morphology is based on repetitive calculations for a wide range of data, resulting in high execution time and memory requirement. Hence, hardware acceleration presents one of the most appropriate solutions to overcome this limitation. In this paper, we propose an efficient hardware architecture aiming to increase performances of morphological gradient computation for grayscale images. The architecture exploits both intra-level and inter-level parallelisms to speed up calculations. In addition, it processes data on stream which decreases memory utilization. The architecture allows extracting the standard edge gradient as well as the external and internal edge gradients at the desired magnitude and thickness level. Unlike most of existing works, the proposed architecture supports reconfigurable shapes and sizes of structuring elements. It is successfully implemented on FPGA. The proposed architecture can process data at a throughput of 356 Mpx/s. Accordingly, a high frame rate for moderate size of structuring elements and high image resolution is achieved.