A high speed bulk CMOS C/SUP 2/L microprocessor

Abstract

The CDP 1802, single-chip, 8-bit microprocessor is fabricated in C/SUP 2/L, or closed COS/MOS logic, a new structural approach to high-speed bulk silicon COS/MOS logic. In this self-aligned silicon-gate CMOS technology, the gate completely surrounds the drain providing transistor aspect ratios which maximize the transconductance to capacitance ratio and thus allow high on-chip speed. Generally, standard 6-/spl mu/m channel length C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately four times faster than standard CMOS. High density 5-/spl mu/m channel length devices further improve area and speed by factors up to 1.5. The fabrication sequence for C/SUP 2/L devices requires six photomasks (one less than standard CMOS).