A high resolution time-to-digital converter using two-level vernier delay line technique

Abstract

This paper describes the design of time-to- digital converter ( TDC ) with two level Vernier delay line (VDL) , which is used to solve the problem of long conversion time in single level VDL and reduce the number of elements. The time interval to be measured between two pulse signals is separated into integral period part and non-integral period part by control circuit. Integral part is sent to counter, and non-integral parts are sent to the two level VDL. In the first VDL can get coarse resolution ( Tclk/N ) , and the signals will be transmitted to the second VDL by the proposed interface circuit. Fine resolution (Tclk/N2) can be gotten in the second VDL. Finally, readout circuit converts thermal code to binary code and do the subtraction to obtain the final results. The bias voltage of delay elements in VDL is controlled by DLL, this makes delay elements can stably provide two kinds of delay time for VDL. The circuit is realized with the process of TSMC CMOS 0.18 um 1P6M. 200 Mhz clock frequency is chosen in the circuit. From the simulation results, the conversion time is smaller than 5 clock periods, the maximum time can be measured is 75 ns. After the fine resolution is modified to 29.6 ps, the DNL is within -0.33LSB - +0.69LSB , and INLis within +0.47LSB - +1.08LSB.