A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

Abstract

In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwidth product of 10 MHz when driving a 150 pF load capacitance. Good robustness is achieved under PVT variations, in particular for voltage gain, offset voltage, and phase margin. State-of-the-art small signal figures of merit and limited area footprint are key characteristics of the proposed amplifier.