A high-frequency memristor emulator: A novel design based on current mode analog building blocks

In current mode analog circuit design, current differencing unit is widely used at the input stage of the current mode analog building blocks. The low input impedance current differencing unit is excellent for current mode circuit realization. In the current study, the positive feedback is used for reducing the input impedance of current differencing unit. The proposed current differencing unit is tested at the input stage of the ZC-CDBA (Z copy current differencing buffered amplifier) recently published as a current mode analog building block. The proposed circuit for ZC-CDBA is verified with the KHN analog filter application. The circuit simulations are verified by using BSIM3 0.18 μm level-7 SPICE parameters.

This article presents a novel charge-controlled memristor emulator circuit. The proposed memristor emulator utilizes a single Current Follower Transconductance Amplifier (CFTA) as an active current mode analog building block and a grounded capacitor as a passive element. The circuit presented follows all the fingerprints of an ideal memristor. It operates in both incremental as well as decremental mode. The functional performance of the emulator circuit is verified at different operating frequencies and performs well up to <italic>9 MHz</italic>. The theoretical and non-ideal analyses are verified for the proposed emulator. Moreover, Monte Carlo sampling and non-volatility analysis are performed to investigate the robustness of the emulator circuit. The functionality of the proposed model has been verified through PSPICE simulation using TSMC <italic>0.18</italic> <inline-formula> <tex-math notation="LaTeX">$\mu m$ </tex-math></inline-formula> CMOS technology at the supply voltage of <inline-formula> <tex-math notation="LaTeX">$\pm 1.2~V$ </tex-math></inline-formula>. The experimental confirmation of the presented circuit is also performed by building a breadboard micromodel using ICs CA3080 and AD844AN. Memristor based Chua&#x2019;s circuit model is included as one of its applications.

For some complex mixed-signal Integrated Circuits (ICs) testing for quality assurance is approaching the manufacturing costs. Mixed Signal IPs have Analog and Digital building blocks which are integrated to create a top-level IP block. Analog building blocks use variety of active and passive devices which will have different design rules to be followed to meet the manufacturing requirements. With lower process node, the number of design rules is increasing exponentially. These rules put lots of constraints on device placements. Lack of layout designs in the early phase of new process nodes inhibits the layout designers to validate all the design rule requirements and the violations are found later in the design cycle. Every time a new Process Design Kit is released with new design rules, the layout design teams have to validate the changes on live designs leading to lost design cycles. One of the solutions involved is to create layout test structures using different device types with all combinations available on a given process node and test structure to test integration guidelines given by SoC. These test structures will enable layout designers to qualify the design rules and then identify the valid placement and integration specifications. These can also be used to Quality Assurance (QA) of new Process Design Kit(PDK) before providing PDK to the design engineers. This will reduce the overall design cycle time by testing the design kits and provides guidelines to the layout designers for creating the layouts.

This paper presents a proposal for a new analog building block with more versability than the Burr-Brown OPA 660: it covers all the OPA 660 possibilities and allows other specific applications as the CCII-, fully differential OTA and universal amplifier-the operational floating conveyor. The applications presented here prove that with two more current mirrors and some supplementary connections one could obtain an important versatility enhancement.

An analogue current mode design methodology is presented for the implementation of binary associative memories. Thus, by using the Hamming feedforward network as an example of a binary associative memory and efficiently mapping it into two CMOS-VLSI building block configurations, a prototype artificial neural network (ANN) is developed. The IC building blocks utilize the characteristics of the subthreshold region and converge to a classification in one pass, requiring no feedback. The result is an analog network with the desirable features of high integration, low circuit complexity, and low power dissipation. >

In this article, we have proposed a grounded memristor emulator model using CCII and VDIBA blocks. The proposed circuit also uses one resistor and one capacitor along with analog building blocks. The presented memristor emulator operates up to 25 MHz. The proposed memristor is simulated using Cadence Virtuoso 180 nm CMOS parameter. The proposed memristor works at ± 0.9 V and the power consumption is 2.4 mW. The adaptability of the memristor emulator during circuit implementation is tested by connecting the memristors in parallel.

Single DVCCTA based high frequency incremental/decremental memristor emulator and its application

The 0.4µm CMOS receiver IC for the FLEXTMpaging system is designed and fabricated to integrate analog and digital building blocks onto a single chip in the near future. To study the influences of the digital switching noise into analog building blocks, a digital noise source block is implemented with the receiver IC. The receiver IC contains a 2nd mixer, a limiting amplifier, a detector, base-band amplifiers and a bit rate filter, and satisfies the specification of the FLEXTMpaging systems. The receiver IC consumes 2.8mW(1.4mA × 2.0V) in the receiving mode.

An emulator circuit of Memristor, Memcapacitor, and Meminductor commonly termed as mem-elements has been demonstrated in this article. The circuit has been realized using the technique of current mode, which provides better performance over voltage mode counterparts. The current mode analog building blocks, along with a few passive components, have been used in the presented circuit implementation. The fingerprint characteristics have been observed in both simulation and experimental results, validating the theoretical analysis. The robustness of the presented design has been supported by performing different types of analysis like process corner, temperature, and non-volatility behavior. The mem-elements emulator design has been simulated using $0.18~\mu \text{m}$ TSMC process parameter, and ±1.2 V power supply has been used. The commercial ICs AD844 and CA3080 are used for the experimental demonstration of the proposed mem-elements design by making a prototype on a breadboard. A layout area of $4829~\mu \text{m}^{2}$ , $8098~\mu \text{m}^{2}$ , and $8061~\mu \text{m}^{2}$ respectively is required for the Memristor, Memcapacitor, and meminductor circuit. The power consumed by the mem-elements circuit is also provided. A chaotic has been implemented using mem-elements to show the usefulness of the emulator design.

Reliability and availability are crucial in smart transformers (ST), and power routing in a modular design can reduce thermal stress of power semiconductors and thereby prevent failures. A desired feature of power routing is the independent control of the thermal stress within the ST architecture, which also includes the maximum unbalanced loading of the medium-voltage side converter. The currently employed algorithms, including the multi-frequency power routing, obtain an inherent coupling of the thermal stress between medium-voltage alternating currents (MVac) building blocks and low-voltage direct current (LVdc) building blocks as well as a limitation in the maximum imbalance for the loading of the MV side converter. For overcoming these limitations, discontinuous pulsewidth modulation is combined with power routing for decoupling the thermal behavior of the MVac and the LVdc building blocks and increasing the maximum achievable imbalance of the MV side converter. The algorithm is analyzed and implemented on an experimental test bench with junction temperature measurement. In addition, a study case is carried out to demonstrate the impact of the proposed method on the lifetime of different building blocks.

This paper introduces a new scheme of oscillator realisation and its implementation in the form of a novel circuit, which requires two current mode building blocks and two grounded capacitors, besides two resistors. The proposed circuit generates two sinusoidal voltage outputs and operates on ±2.5 V supply voltage. The parasitic and non-ideal analysis of the proposed circuit is given. PSPICE simulation results are included in support of the proposed theory. The new proposed circuit is compatible to CMOS technology. Several possible applications are suggested as conclusive discussion to justify the new advance.

Recent implementations of switched-capacitor circuits using current conveyors show promising results. The circuits derived provide the opportunity to explore other uses of the versatile current conveyor in developing additional signal processing building blocks. In this paper we present building blocks that can be used for both filtering and non-filtering applications. Experimental results from the new building blocks demonstrate they work as predicted by the theory.

In this paper, a resistorless improved wave active filter (WAF) is presented using a comparatively new current-mode building block, namely extra X current-controlled current conveyor (EX-CCCII). The proposed wave active filter is designed in the current mode. The incident and reflected waves are used for designing the basic wave active elements, namely series and shunt inductors (L) and capacitors (C). The novelty of the circuit is that the mathematical operations like lossy integrator, unity gain amplifier, summation, and subtraction, required to realise the wave active elements, are accomplished by judiciously using the port relationships of EXCCCII. As a result of which the proposed circuit is compact and uses only two EXCCCIIs and one grounded capacitor for the realisation of wave elements (L and C). One 3rd and one 4th order Butterworth wave active filters are designed using EX-CCCII-based wave elements and simulated in cadence using 0.18 µm TSMC CMOS technology. The comparison indicates that the proposed WAF uses minimum numbers of analog building blocks (ABBs) and consumes the least power; moreover, the performances such as noise, percentage total harmonic distortion (%THD), and electronic controllability of cut-off frequency of the filters are also reported. Abbreviations: ABB: analog building block; FDNR: frequency-dependent negative resister; WAF: wave active filter; THD: total harmonic distortion; OTA: operational transconductance amplifier; CFOA: current feedback operational amplifier; VDTA: voltage differencing transconductance amplifier; OTRA: operational transresistance amplifier; CCDDCCTA: current-controlled differential difference current conveyor transconductance amplifier; DVCCCTA: differential voltage current-controlled conveyor transconductance amplifier; DVCCTA: differential voltage current conveyor transconductance amplifier; EX-CCCII: extra X current-controlled conveyor

The paper presents a high speed and a high resolution pipelined A/D converter relying on a current mode technique. The A/D converter structure is composed of current mode building blocks. All building blocks have been designed, then manufactured, in CMOS AMS 0.8 /spl mu/m technology and measured to verify the proposed concept.

A new current mode building block named voltage and current gain second generation current conveyor (VCG-CCII) is introduced. The voltage and current buffers of the standard CCII are replaced by voltage and current amplifiers with tunable gains so to obtain an extremely flexible and versatile building block. The VCG-CCII can be used in place of the standard CCII in impedance conversion applications so to utilize only one active component. A circuit implementation in a standard 0.35 μm CMOS process is presented and used to multiply, as an example, a 10 pF capacitor by a factor tunable from 1 up to about 3100, achieving a capacitance multiplication for more than 6 decades frequency range (from 0.15 to 865 KHz for the highest multiplication factor).