A hardware architecture for real-time edge detection based on interval type-2 fuzzy logic

Abstract

This work presents the design of a hardware architecture of interval type-2 fuzzy edge detector, performing fuzzy edge detection algorithm at high fidelity to the theoretical model and robustness, at a reduced computational time through hardware design strategies as parallelism and pipelining. Edge detection is an important processes in digital processing of images, but its high computational cost limits real-time applications. Fuzzy-Edge detectors have shown better performance than conventional methods, but at an even higher computational cost. The proposed hardware architecture is adaptable to different context of contrast or brightness without modification of the structure, by means of editable registers; it is described in VHDL that is a Hardware Description Language and synthesized in the Xilinx FPGA Spartan 6 through the Xilinx ISE design platform. The described hardware architecture achieves real-time processing for up to 48 frames per second (FPS), for an image of 1280 by 720 pixels, requiring 44.2 million of Fuzzy Logic Inferences per Second (FLIPS). The proposed architecture is tested to document its processing rate, its fidelity is evaluated and compared to the theoretical algorithm, and sample fuzzy edge detection is reported under controlled perturbations.