Abstract

A general purpose median filter configuration consisting of two single chip median filters is proposed. One of the chips is designed for applications requiring variable word-length and variable window size, whereas the other is for real-time applications. The architectures of the chips are based on odd/even transposition sorting. The chips are implemented in 3- mu m M/sup 2/CMOS using full-custom VLSI design techniques. The chips together with a reasonable external hardware can be used for the realizations of many median filtering techniques. The VLSI design procedure of the chips and their applications to different median filtering techniques for image processing are presented. >

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