Abstract
This paper introduces a gain enhancement technique for monolithically integrated antennas. Such devices can suffer from gain dips within their operating bandwidth due to standing waves arising in the die or caused by interactions with other on-chip components. In this work, it is shown how these effects can be significantly mitigated by parasitically coupling square Split Ring Resonators (SRR) to the fed antenna. The SRRs geometry and their coupling with the master antenna can be set in such a way that they create an additional resonance that cancels gain drops and improves impedance matching. The proposed configuration has been validated using a W-band monopole antenna in a standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.13~\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS process. Thanks to the proposed approach, it was possible to compensate a gain drop of about 7 dB at about 85 GHz. As a result, the experimental assessment showed a maximum measured antenna gain of 1.61 dB at 81.5 GHz and an operating bandwidth from 77 to 87 GHz.
Highlights
A Gain Levelling Technique for On-Chip Antennas Based on Split-Ring ResonatorsCARMINE MUSTACCHIO , (Member, IEEE), LUIGI BOCCIA , (Senior Member, IEEE), EMILIO ARNIERI , (Member, IEEE), AND GIANDOMENICO AMENDOLA , (Senior Member, IEEE)
In order to cope with emerging high-speed communication requirements, upcoming wireless networks are expanding to new portions of the electromagnetic spectrum
REFERENCE MONOPOLE DESIGN The proposed work was developed employing a standard 0.13 μm SiGe BiCMOS process, namely the SG13S technology provided by IHP Microelectronics which offers 5 thin and 2 thick metal layers referred to as TM1 (2 μm) and TM2 (3 μm) (FIGURE 1)
Summary
CARMINE MUSTACCHIO , (Member, IEEE), LUIGI BOCCIA , (Senior Member, IEEE), EMILIO ARNIERI , (Member, IEEE), AND GIANDOMENICO AMENDOLA , (Senior Member, IEEE). Dipartimento di Ingegneria, Informatica, Modellistica, Elettronica e Sistemistica, dell’Università della Calabria, 87036 Rende, Italy.
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