Abstract
The reconfigurable cell array (RCA) architecture and its implementation are presented in this article. A distinctive feature of this architecture is its dual mode of operations. A reconfigurable cell in this array can operate in either blocking mode or non-blocking mode. This makes it suitable for efficient dataflow computation. This architecture is designed for high-throughput applications of software-defined radio (SDR) using fully pipelined and wavefront computation with fast dynamic reconfiguration. The RCA is part of a SDR chip and is responsible for the high-throughput, intermediate-frequency processing such as digital up and down conversion. In addition to the processing cells, the RCA also includes finite-state machine controllers for data stream management and distributed memory elements for stream data storage. The RCA, when combined with the programmable digital signal processor array, forms a powerful system for the SDR.
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