Abstract
This paper presents DG based droop controlled parallel inverter systems with virtual impedance considering the unequal resistive-inductive combined line impedance condition. This causes a reactive power sharing error and dynamic performance degradation. Each of these drawbacks can be solved by adding the feedforward term of each line impedance voltage drop or injecting the virtual inductor. However, if the line impedances are high enough because of the long distance between the DG and the PCC or if the capacity of the system is large so that the output current is very large, this leads to a high virtual inductor voltage drop which causes reductions of the output voltage and power. Therefore, the line impedance voltage drops and the virtual inductor and resistor voltage drop compensation methods have been considered to solve these problems. The proposed method has been verified in comparison with the conventional droop method through PSIM simulation and low-scale experimental results.
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