Abstract

Proposes a novel discrete wavelet transform (DWT) architecture which is fully scalable, flexible, and modular. This architecture is bit serial, and therefore, has low hardware complexity and low power requirement. Nevertheless, because of its particular structure, it operates on-the-fly (i.e., it does not require wait cycles between consecutive input samples). Moreover, a very small hardware overhead can upgrade the architecture to compute also the inverse DWT ("double-face" utilization). Hardware complexity and computing performance are analyzed in detail.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.