A Direct-Capacitance-Conversion FeRAM Characterization Platform for Enabling Non-Destructive 3-D Ferroelectric Capacitor Readout

A continuous-time (CT) sigma-delta ($\Sigma\Delta$) modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter is presented and implemented in tsmc 0.18 um CMOS technology. The proposed $\Sigma\Delta$ modulator with RF receiver comprises a third-order RC operational-amplifier-based loop filter, a 4-bit internal quantizer operating at 160 MHz, three DACs operating at 1.2 V supply voltage and2.4GHz receiver for wireless respiratory detection. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The proposed design incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. Measured results proposes that the $\Sigma\Delta$ modulator achieves SNDR of 56.5 dB and ENOB of 9.1-bit over a 10 MHz band at an over-sampling ratio (OSR) of 8. The proposed receiver antenna proposed return loss is lower than 2. The proposed modulator dissipates 10.1 mW and including pads, the chip area is $0.363mm^{2}$.

A CT (continuous-time) sigma-delta modulator (CT ΣΔM) clocked at 128 MHz with a hybrid active-passive loop filter is presented for WCDMA applications. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. To erase the summation amplifier used in the CIFF (chain of integrators with weighted feedforward summation) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 µm 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of −48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 × 0.6) mm2.

– On-chip DC-to-DC converters are critical to ensure regulated voltage for a variety of DC applications, including automotive and personal computer products. The converters have historically been limited to low power applications due to the size and cost constraints involved with the desire to have the converters integrated with the application circuit. The latest technology involves using switched-capacitors to allow for lower cost and monolithic integration. A new DC-to-DC converter design, utilizing a ferroelectric (FE) capacitor is researched, fabricated and tested. The inclusion of a FE, switched-capacitor results in an increase in the converter's output voltage due to the high dielectric constant (high-k) of the capacitor in conjunction with the resulting switching current as the polarization of the capacitor is reversed. In fact, the FE capacitor's effective capacitance resulting from the polarization switching provides the same behavior as a linear capacitor that is approximately 10 times the size (with respect to capacitance) as the FE capacitor. A proposed ferroelectric-based DC-to-DC step-down converter is analyzed, simulated, fabricated and tested. The results show the FE capacitor-based converter provides an output voltage and output impedance advantage over linear capacitor-based converters for equivalent capacitance levels.

Transient negative differential capacitance (NC), the dynamic reversal of transient capacitance in an electrical circuit is of highly technological and scientific interest since it probes the foundation of ferroelectricity. In this letter, we study a resistor-ferroelectric capacitor (R-FeC) network through a series of coupled equations based on Kirchhoff's law, Electrostatics, and Landau theory. We show that transient NC in a R-FeC circuit originates from the mismatch between rate of free charge change on the metal plate and that of bound charge change in a ferroelectric (FE) capacitor during polarization switching. This transient charge dynamic mismatch is driven by the negative curvature of the FE free energy landscape. It is also analytically shown that a free energy profile with the negative curvature is the only physical system that can describe transient NC during the two-state switching in a FE capacitor. Furthermore, this transient charge dynamic mismatch is justified by the dependence of external resistance and intrinsic FE viscosity coefficient. The depolarization effect on FE capacitors also shows the importance of negative curvature to transient NC. The relation between transient NC and negative curvature provides a direct insight into the free energy landscape during the FE switching.

Ferroelectric tunnel junctions are promising towards high-reliability and low-power non-volatile memories and computing devices. Yet it is challenging to maintain a high tunnelling electroresistance when the ferroelectric layer is thinned down towards atomic scale because of the ferroelectric structural instability and large depolarization field. Here we report ferroelectric tunnel junctions based on samarium-substituted layered bismuth oxide, which can maintain tunnelling electroresistance of 7 × 105 with the samarium-substituted bismuth oxide film down to one nanometer, three orders of magnitude higher than previous reports with such thickness, owing to efficient barrier modulation by the large ferroelectric polarization. These ferroelectric tunnel junctions demonstrate up to 32 resistance states without any write-verify technique, high endurance (over 5 × 109), high linearity of conductance modulation, and long retention time (10 years). Furthermore, tunnelling electroresistance over 109 is achieved in ferroelectric tunnel junctions with 4.6-nanometer samarium-substituted bismuth oxide layer, which is higher than commercial flash memories. The results show high potential towards multi-level and reliable non-volatile memories.

Advances have been made in the electronic characterization and analysis of thin-film ferroelectric (FE) memory capacitors using capacitance vs. voltage (C-V) measurements. A mathematical model of the small-signal electrical behavior of the FE capacitor has been developed. This analysis shows that the small-signal characteristics of the FE capacitor are largely determined by the space charge concentrations at the ferroelectric to contact interface. These space charge regions have an adverse effect on the permittivity, coercivity and switching characteristics of the ferroelectric capacitor. These results will contribute to improving ferroelectric processing, appraising the quality of ferroelectric devices, and developing device models of the ferroelectric memory capacitors for use in circuit design.

Ferroelectric (FE) capacitor is a critical electric component in microelectronic devices. Among many of its intriguing properties, the recent finding of voltage drop (V-drop) across the FE capacitor while the positive charges flow in is especially eye-catching. This finding was claimed to be direct evidence that the FE capacitor is in negative capacitance (NC) state, which must be useful for (infinitely) high capacitance and ultralow voltage operation of field-effect transistors. Nonetheless, the NC state corresponds to the maximum energy state of the FE material, so it has been widely accepted in the community that the material alleviates that state by forming ferroelectric domains. This work reports a similar V-drop effect from the 150 nm thick epitaxial BaTiO3 ferroelectric thin film, but the interpretation was completely disparate; the V-drop can be precisely simulated by the reverse domain nucleation and propagation of which charge effect cannot be fully compensated for by the supplied charge from the external charge source. The disappearance of the V-drop effect was also observed by repeated FE switching only up to 10 cycles, which can hardly be explained by the involvement of the NC effect. The retained reverse domain nuclei even after the subsequent poling can explain such behavior.

This article proposes a low spurious noise and fast-transient-response buck converter with second-order continuous-time delta-sigma modulator (CT-DSM). The DSM technique has the superiority of oversampling and the characteristics of noise shaping to reduce spurious noise and speed up transient response. Moreover, the transient response eruption technique uses a dynamic current compensator to accelerate the transient response. Therefore, the proposed CT-DSM buck converter reduces spurious noise, reduces the output harmonic tones, and accelerates transient response, but it keeps high efficiency, low noise, and low ripple of the traditional switching converter. The proposed DSM buck converter is fabricated in TSMC 0.35 μm 2P4M CMOS process with a chip area of 1.32 ×1.38 mm. The measurement results show that the peak noise power is -70 dBm across output spectrum, which is -10 dBm lower than a traditional CT-DSM buck converter. When the load current changes from 50 to 500 mA and from 500 to 50 mA, the transient responses are both 4 μs, which are 7 μs faster than the traditional CT-DSM buck converter. The maximum output overshoot voltage is 20 mV, the output voltage ripple is 10 mV, and the conversion peak efficiency 90.4% at the output voltage of 2.4 V. These characteristics keep the same performances as or even better than the traditional CT-DSM buck converter.

Ferroelectric materials have a spontaneous polarization that can point along energetically equivalent, opposite directions. However, when ferroelectric layers are sandwiched between different metallic electrodes, asymmetric electrostatic boundary conditions may induce the appearance of an electric field (imprint field, Eimp) that breaks the degeneracy of the polarization directions, favouring one of them. This has dramatic consequences on functionality of ferroelectric-based devices such as ferroelectric memories or photodetectors. Therefore, to cancel out the Eimp, ferroelectric components are commonly built using symmetric contact configuration. Indeed, in this symmetric contact configuration, when measurements are done under time-varying electric fields of relatively low frequency, an archetypical symmetric single-step switching process is observed, indicating Eimp ≈ 0. However, we report here on the discovery that when measurements are performed at high frequency, a well-defined double-step switching is observed, indicating the presence of Eimp. We argue that this frequency dependence originates from short-living head-to-head or tail-to-tail ferroelectric capacitors in the device. We demonstrate that we can modulate Eimp and the life-time of head-to-head or tail-to-tail polarization configurations by adjusting the polarization screening charges by suitable illumination. These findings are of relevance to understand the effects of internal electric fields on pivotal ferroelectric properties, such as memory retention and photoresponse.

A nondestructive readout (NDRO) scheme without polarization reversal in a ferroelectric random access memory (FeRAM) is proposed as a solution for extending the number of readout cycles. However, the readout signal in an NDRO FeRAM is so small that the NDRO operation is sensitive to deformation of the P−V hysteresis loop, which is a manifestation of imprint phenomena. In order to minimize the imprint effect in the NDRO FeRAM, we introduced an asymmetrical polarization programming scheme. Using this scheme, we can expect an extended number of readout cycles more than 1016 regardless of the imprint phenomena in ferroelectric capacitors.

Gallium-doped hafnium oxide (HGO) exhibits excellent ferroelectricity with remarkable reliability and improved endurance characteristics. However, the requisite high-temperature annealing (>600 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C) poses challenges for CMOS back-end-of-line (BEOL) integration. To achieve ferroelectric (FE) HGO at low temperatures (below 400 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C), we carried out an in-depth analysis on the role of N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> flow during rapid thermal annealing (RTA) on ferroelectricity at 400 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. Low-N<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>-flow-rate annealing under reduced pressure lowers the energy barrier for stabilizing the FE orthorhombic phase (o-phase) in HGO, though at the expense of cooling efficiency. Strategic flow parameter optimization enables FE for the HGO capacitor under BEOL-compatible annealing conditions. In addition, the FE behavior of HGO films with different Ga doping concentrations was investigated. The identified Ga doping window (4.17–9.09 atomic%) redefines the phase stability criteria for 10 nm HGO FEs. The remnant polarization (2<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>r</i></sub>) of 24.8 μC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup> was achieved for HGO samples with 6.14 atomic% Ga processed at 400 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. Furthermore, due to the decrease in process temperature, the devices exhibit robust performance, including low leakage current and high endurance (>10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>9</roman></sup>). This work establishes a BEOL-compatible hafnium-based FE material system through low-temperature process engineering.

The approach taken in the development of this Ferroelectric Material Test Chip (FMTC-3861) was to design test structures which allow for the extraction and evaluation of critical process and device parameters, as well as making a judgement concerning the relative magnitude of their effects on overall ferroelectric device performance. This paper discusses the design of the FMTC-3951 developed by Harris to evaluate the performance level of a three micron ferroelectric capacitor technology. Numerous electrical and parametric test structures are contained in FMTC-3861, including: various process monitoring, defect density, and ferroelectric capacitor test structures. Ferroelectric thin film electrical and material characteristics such as polarization, fatigue, aging, switching, TDDB, DC breakdown, leakage, etc. can be studied as a function of material deposition methodology and crystalline stoichiometry, capacitor area, capacitor layout orientation, capacitor geometric shape, electrode type and configuration, and parasitic electric fields.

In this work, CMOS-compatible ferroelectric (FE) $\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ capacitor based processing-in-sensor (PIS) hardware is proposed and experimentally demonstrated for the first time, realizing zero-power sense and inference with in-situ motion detection and four-quarter multilevel multiply-accumulation (MAC). By utilizing the intrinsic pyroelectric effect and the multi-domain features of F$\mathrm{E}-\mathrm{H}\mathrm{f}\mathrm{O}_{2}$, the proposed non-volatile PIS device can experimentally implement local multiplication of sensing input signal and polarization-modulated signed weight by only one FE capacitor, without the need of sensing power or extra peripheral differential circuits for motion detection, along with the advantages of low operation voltage (2V), high endurance (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> cycles), long retention (10 years) and good consistency. Besides, the optimized fabricated FE- $\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ PIS device also exhibits the record highest pyroelectric sensitivity among $\mathrm{F}\mathrm{E}-\mathrm{H}\mathrm{f}\mathrm{O}_{2}$ materials. Furthermore, the infrared (IR) response of the proposed FE-PIS array is also experimentally demonstrated, enabling multilevel signed MAC with high linearity for IR motion detection. Based on proposed FE-PIS design, motion pattern recognition and further data compression tasks with high accuracy (99%) are realized, showing its great potential for edge AI.

This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO's input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO's input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while achieving 63.1-dB dynamic range in 480 kHz-20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors' best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.