Abstract
A digitally controlled frequency-doubling phase-shifter architecture is presented for the implementation of multiple-antenna GHz transceiver systems. It takes a 1.75GHz input and produces two phase-shifted outputs at 3.5GHz. It consists of a Delay Locked Loop (DLL) followed by symmetric XOR frequency doublers and phase interpolators. The phase shifter prototype in 90nm standard CMOS has a phase shift range of 360° with a resolution of 22.5° and an INL < 12° (< 4° with external adjust), and consumes 55mW from a 1V supply.
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