Abstract
The paper studies the problem of developing a high-speed number correction device in computing systems operating in the basis of non-positional arithmetic in residual classes. The topicality of the problem is necessitated by the search of solutions allowing reducing the time for digital processing of signals in non-positional neuroprocessors. The device allows correcting errors with single and multiple control bases of the residue system. The work presents the structure of the unit that realizes the paired zeroing on numbers in the system of residual classes. It was demonstrated that the suggested solutions allow appreciably reducing the time consumption by digital processing of signals in neuroprocessors destined for operations of summation and multiplication.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
