A design assembly framework for FPGA back-end acceleration

Abstract

There are well known cases where FPGAs provide high performance within a modest power budget, yet unlike conventional desktop solutions, they are oftentimes associated with long wait times before a device configuration is generated. Such long wait times constitute a bottleneck limiting the number of compilation runs performed in a day; thus limiting to FPGA adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Fifteen International Workshop on Logic and Synthesis (IWLS) 2005 benchmark designs and five large designs are used to evaluate qFlow. Experiments show up to 10× speed-ups using the proposed paradigm compared to vendor tool flows.