A Design Approach of Mitigating Single Event Upset for On-Chip Memory Based on SoC FPGA

Abstract

To solve the problem of dual-core communication error in SoC FPGA which caused by SEUs (Single Event Upset) for space applications, an approach of OCM (On-Chip Memory) reinforcement for mitigating SEUs is designed in this paper. Combined the Software EDAC (Software-Implemented Error Detection and Correction) technology using Hsiao code and the hardware resource of SGI (Software Generated Interrupt) in Zynq-7000, the design approach has the capability to correct the single-bit error and detect the double-bit error when CPUs access OCM. Furthermore, dual-core processors can write back to OCM synchronously when single bit error occurred. The verification result shows that the design approach has the advantages of low delay, high reliability and flexible design. Also, it can avoid the conflict of data write-back when the dual-core processors access OCM. The design approach makes full use of on-chip resources, it has no requirement of additional hardware resources to improve the capability of mitigating SEUs for dualcore communication in SoC FPGA.