Abstract
We describe the design of an undergraduate compilers course for computer engineering students in which the projectis to write a simulator and synthesizer for (a subset of) VHDL. The traditional project for such a course is to write a compiler for (a subset of) some procedural programming language. The choice of source language is superficially intended to drive student engagement for computer engineers. The main pedagogical advantage of this project is that item bodies a learning progression: repetition with increasing complexity.This project involves two additional languages: a regular language for boolean waveforms (used for circuit simulator inputand output), and a context-free language for boolean formulas. Parsing and transformations are performed on these simpler languages before attempting them on the subset of VHDL. At the end of the project the students can simulate and synthesize simple circuits such as a ripple-carry adder or a multiplexer.
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