Abstract
A 12-bit video speed pipelined switched capacitor analog-to-digital converter (ADC) has been implemented in a 0.5 µm standard CMOS process. It operates from a single 2.6–3.3V supply, dissipates 23mA (independent of supply voltage) at 20 MSPS and occupies only 1.1mm ^2. A 61dB SINAD (f_in e 4.5 MHz) and an effective resolution bandwidth of 9 MHz is achieved.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
