Abstract
The fabrication of complementary metal oxide semiconductor (CMOS) structures with praseodymium oxide or titanium-doped praseodymium oxide layers as integrated high- gate dielectrics requires the development of a process-compatible etching recipe. Different wet-etching processes in acid-based chemistry were evaluated and solutions of diluted sulfuric acid were identified as suitable etchants for and layers on Si substrates. Metal-oxide-semiconductor stacks with poly-Si as the potential gate electrode were patterned with the help of tetramethyl ammonium hydroxide as the selective etchant attacking the poly-Si gate electrode material but not the underlying Pr-based high- gate dielectric layers.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
