Abstract
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula> -domain model, supporting any frequency division ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> and CSL (or IL) strength <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> . The new theory sheds light not only on all IL-like PN phenomena (chiefly, its “loop” bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the “loop” cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75—26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.
Highlights
T harmonic extractors (HEs) emerging 5G/6G and other high-speed communication standards (e.g., WIFI-6/7) pose very tough phaseManuscript received March 23, 2021; revised July 30, 2021; accepted August 16, 2021
phase noise (PN) of the reference and charge-sharing locking (CSL) was characterized by an R&S 2-Hz–85-GHz FSW Signal and Spectrum Analyser, while Keysight E5052B was used to measure the PN at the Q-digitally controlled oscillator (DCO) output
The actual reference jitter seen by the CSL switch accounts for both the external reference source and its on-chip distribution path, which is estimated at 113 fs (= 812 + 792 fs) in total
Summary
T HE emerging 5G/6G and other high-speed communication standards (e.g., WIFI-6/7) pose very tough phase. The main challenges of the sampling-based PLLs with high PD gain stem from the consequent limited phase detection range, requiring an additional frequency-locked loop (FLL) to enhance their process, voltage, and temperature (PVT) robustness [3]. Irrespective of the choice of analog FTL (or FLL), the analog loop filter usually occupies a large area [6], [7], [17], resulting in high costs in advanced CMOS Another challenge in IL oscillators (ILOs, including phase-realigned oscillators) is how to control the “loop” bandwidth in order to reduce the effect of the reference PN on the optimized rms jitter.
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