A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers

Abstract

Circuit switching is a way to minimize network latency and maximize network bandwidth when a limited number of source-and-destination pairs exchange messages which are predictable. Although there are a large number of studies of optical circuit switching (OCS) on HPC systems and datacenters, it is still not mature. In this context, we explore the use of electrical circuit switching (ECS) for the low-latency purpose on HPC systems and datacenters. ECS has the same link bandwidth as existing electrical packet switched networks, and inherits quick update of input-and-output connections from electrical switches. We develop a network topology generator for ECS to minimize the number of time slots optimized to target applications whose traffic patterns are predictable. By performing a quantitative discrete-event simulation, we present that an ideal ECS network outperforms counterpart EPS networks. Evaluation results show that the minimum necessary number of slots (MNNS) can be reduced to a small number in a generated topology while keeping resource amount less than that in a standard mesh network.