A Broadband Bonding-Wire Compensation Technique Using Lowpass Filter Topology and Elliptical Slot Structure for High-Speed Differential Interconnections

ABSTRACTIn this article, a novel very compact DGS lowpass filter (LPF) and reconfigurable bandpass filter are proposed. The designed filter consists of one T‐DGS resonator, which is excited by 50 ohm microstrip line, placed on top layer between the input and output of the proposed structure. The selected filter topology has several advantageous compared with the other previous works such as the compactness and its simple design. The addition of compensated patch capacitor improves the low insertion loss and ultra‐wide stopband with 15 dB attenuation from 2.2 to 3.6 GHz. The size of the proposed single T‐DGS LPF‐BPF is less as (0.023 λg × 0.044 λg) with λg = 0.263 m. The tunable bandpass filter (BPF) is extracted from LPF topology using variable Chip Monolithic Ceramic Capacitors and J‐inverter technique. Finally, the measured, EM‐ and field simulation results are presented and discussed. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1142–1148, 2016

This paper presents a modified Doherty configuration with extended bandwidth. The narrow band feature of the conventional Doherty amplifier is discussed in the view of the broadband matching. To extend the bandwidth, the post-matching architecture is employed in the proposed design. Meanwhile, broadband low-order impedance inverters are adopted to replace the quarter-wavelength transmission lines. Low-pass filter topologies are used to realize both the post matching network and the impedance inverters. A modified Doherty Power amplifier was designed and fabricated based on commercial GaN HEMT devices to validate the broadband characteristics of this configuration. The 6-dB backoff efficiencies of 47%-57% are obtained from 1.7 to 2.6 GHz (41.9% fractional bandwidth) and the measured maximum output power ranges from 44.9 to 46.3 dBm in the designed band. In particular, more than 40% efficiencies are measured at 10-dB backoff throughout the operation band.

<span lang="EN-US">In this paper a hardware implementation of single-phase cascaded H-bridge three level multilevel inverter (MLI) using sinusoidal pulse width modulation (SPWM) is presented. There are a few interesting features of using this configuration, where less component count, less switching losses, and improved output voltage/current waveform. The output of power inverter consists of three form, that is, square wave, modified square wave and pure sine wave. The pure sine wave and modified square wave are more expensive than square wave. The focus paper is to generate a PWM signal which control the switching of MOSFET power semiconductor. The sine wave can be created by using the concept of Schmitt-Trigger oscillator and low-pass filter topology followed by half of the waveform will be eliminated by using the circuit of precision half-wave rectifier. Waveform was inverted with 180º by circuit of inverting op-amp amplifier in order to compare saw-tooth waveform. Two of PWM signal were produced by circuit of PWM and used digital inverter to invert the two PWM signal before this PWM signal will be passed to 2 MOSFET driver and a 3-level output waveform with 45 Hz was produced. As a conclusion, a 3-level output waveform is produced with output voltage and current recorded at 22.5 Vrms and 4.5 Arms. The value of measured resistance is 0.015 Ω that cause voltage drop around 0.043 V. Based on the result obtained, the power for designed inverter is around 100W and efficiency recorded at 75%.</span>

An 8-channel switching node with routing function is designed in this paper using a high-performance digital cross-point switch. The throughput of the 8-channel routing node is 10 Gbit/s. Combined with time division multiplexing (TDM) technique, a high-speed optical interconnection network was designed. Using Optical Network Interface Cards (ONIC) and the designed routing node, a two-layer optical interconnection network with structure of ring and star topology is designed. Based on circuits cascading technique, the network can be expanded to meet the request of large scale data communication with low communication latency.

In printed circuit boards (PCB), the selection of surface finish is a balance of cost, performance and material compatibility consideration. When the operating frequency is in gigahertz range, the signal loss in interconnects has stronger dependence on the material composition of traces, surface finishes, substrates, and geometry of the traces. Skin effects, frequency dependent dielectric properties and the electrical functioning mechanism are important factors that affect signal integrity. In this work, both measurements and finite element method (FEM) based full wave simulation are used to investigate the effects of hot air solder leveling (HASL) and its alternatives on signal degradation of high-speed interconnect structures. For the microstrip line structure, the loss due to surface finishes is negligible. For the differential mode coupled microstrip lines, the loss increment resulted from surface finish can be up to 50%∼200% at 10 GHz. Surface finish caused signal loss must be carefully considered for differential mode interconnects.

With the advancement of semiconductor technologies, packaging interconnect becomes one of the bottlenecks in high-performance devices. The paper deals with high-speed differential interconnect commonly used in the flip-chip ball grid array (Fc-BGA) packages. Layout issues for differential interconnect are first discussed, and the emphasis is put on the investigation on the effects of the discontinuity consisting of via and solder ball on electrical performance. Overall electrical performance of one typical differential pair is characterized and -15dB return loss and -23dB isolation between neighboring pairs are achieved up to 10 GHz. The purposes of this paper are to design and optimize high-speed series differential interconnects used in Fc-BGA packages with the first-round success.

A wideband common-mode (CM) suppression filter for bend discontinuities in differential signaling is proposed. A known approach, using tightly coupled microstrips and providing CM reduction in the frequency range from DC till 6 GHz, is revisited and adapted to interconnect structures with a signal bandwidth (BW) up to 50 GHz. The design’s effectiveness in reducing unwanted mode conversion and its flexibility in terms of the applied signal BW is assessed by means of simulations and measurements. Furthermore, the potential of the filter design for usage with 4-level pulse amplitude modulation (PAM4) signaling schemes is discussed. It is demonstrated that the high frequency implementation of this filter reduces CM noise by 62% and that it can successfully be applied in high speed interconnects using PAM4 signaling for data rates up to 70 Gbps.

JESD204B is the newest industry standard used as the high-speed interconnection between data converter and digital signal processor, which supports serial data transfer rate up to 12.5 Gbps. According to the function requirements for 8B10B decoder in JESD204B protocol, a quad_byte parallel processing method is proposed which can reduce operating frequency of decoding circuit significantly thus result in an easier implementation in low-cost CMOS technology library. Simultaneously, it uses the polarity information to simplify the decoding table thus reduce the circuit area, uses the state control to improve the precision of polarity detection, and uses the parallel topological structure to accelerate the circuit speed. Circuit simulation and synthesization results show that our design has certain advantages at operating frequency and circuit area compared with other typical implementation, fully meeting the requirements of JESD204B protocol.

As one of the most effective methods to inhibit electric power grid harmonics, the technology of Active Power Filter (APF) has been a key subject in the field of power quality control. Currently, research on APF mainly focuses on topology structure and control strategy. A novel topological structure of APF in alpha-beta coordinate is presented based on transformation of three phase static A-B-C coordinate to two phase static alpha-beta coordinate. The topological structure adopts two groups of single-phase inverter as main devices of APF, and can realize transformation of current source from two phases to three phases by using a special transformer connection. Decoupling of the three phase harmonic compensation current is realized directly in circuit structure. Calculation for the control quantity in the new topological structure is performed directly in alpha-beta coordinate, and the results are directly applied to two groups of single-phase inverter system. The repetitive learning control method is suggested to verify the viability of the proposed APF. The simulation results show that the novel active power filter topology is feasible and its compensation effect is quite good even dead time of inventers in existence.

A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmission consists of switching the constant driver current from one wire to one of the two others. There is no need for clocking or synchronisation, as bits are separated by a transition. The chosen data representation makes decoding to a two-phase protocol especially simple. Energy consumption may be reduced by dynamically adjusting bias currents, and thus circuit speed, to match the demand for communication bandwidth. In a 0.7 /spl mu/m CMOS process, communication bandwidth per link is expected to reach 1 Gb/s.

It is difficult to extract a narrow road with a width of only a few pixels from a remote sensing image. In order to solve this problem, it is proposed to process the remote sensing image with super-resolution. This paper extends the details of narrow roads by using the Deep Convolutional Neural Network (DCNN) method. Next, some noise points or roads of error extraction are processed by topological structure. To verify performance of the experimental method, experimental research on open remote sensing image data set is carried out. The experimental result is to compare the original image, super-resolution image, and topology filtering. Experimental results demonstrate that the new method has better effectiveness and superiority over the original remote sensing image.

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz.

In this paper, a new integral equation formulation for via structures is developed for the capacitance extraction between vias and planes. The formulation is initially developed for axially symmetric geometries and then extended to axially asymmetric geometries by changing the circular ring cells to arc cells. The extended method can be used to calculate the shared-antipad via structure, which is widely used in high-speed differential signal interconnects. In addition, the image theory is used to handle inhomogeneous media, and a new technique is given to reduce computational costs for via-to-plane structures based on properties of the capacitance-matrix elements. The proposed method is validated with a commercial finite element method-based tool for several practical via structures. The extracted capacitance is also incorporated into the physics-based via model and validated with full-wave simulations.

This paper demonstrates the differential transmission line interconnect for high-speed global interconnect IP. The interconnect is fabricated using a 180 nm CMOS technology. 4 Gbps signal transmission can be achieved in measurement results. The on-chip transmission line performs faster signal transmission than common RC interconnects

The hybrid filter is a combination of a passive filter and a small-rated active filter, which gives a relatively economical approach comparing to a conventional active filter. The initial cost and the operation switching loss of the filter are proportional to the rating of the active filter. Different structures of passive filters in a hybrid filter have different required ratings of the active part of the hybrid filter. Based on the pervious researches, there are many different topologies of a hybrid filter. They can be mainly classified as: Series-Type, b-Shape and Parallel-Type Hybrid Filters. In this paper, a comparison among different structure topologies of Hybrid Filters is performed. The guidelines are given for the selection of Hybrid Filter topologies. Computed and simulated results show out its validity of the discussion in this paper.