A 9 to 12.1 GHz Sub-Sampling ADPLL based on a Stochastic Flash TDC and a DCO with a "Folded" Common-Mode Resonator Exhibiting less than 90fs Jitter and a peak FoMj of -248 dB in 16nm FinFet CMOS

Abstract

This paper presents a power efficient sub-sampling all-digital phase-locked loop with less than 90fsrms jitter performance. A stochastic-flash time-to-digital converter is utilized and obtains sub-picosecond effective resolution. A "folded" common mode resonator is included within the digitally controlled oscillator to enhance performance while maintaining a compact design. The ADPLL covers 9 to 12.1 GHz (29.4% fractional tuning range). Measured phase noise of -105.2/-109/- 124.85 dBc/Hz at 10.6 GHz for 0.1/1/10 MHz frequency offset respectively. Integrated phase noise lower than -45 dBc was recorded for the whole tuning range for an integration range between 10 KHz to 40 MHz. The ADPLL consumes 15.5 mA from a 0.8 V analog supply and 7 mA from a 0.7 V digital supply, for a total power consumption of 17.3 mW and a peak jitter-power figure-of-merit (FoMj) of -248 dB. Fabricated in 16nm FinFet CMOS, the silicon area is 0.24 mm2.