A 65 nm linear broad-band differential Low Noise Amplifier using post distortion technique

Abstract

The paper describes the design of a differential broadband LNA covering the frequency range from 800 MHz to 5 GHz in 65 nm CMOS technology. The work proposes a novel linearization technique for high-frequency wide-band applications using an active feedback as post-distortion. The technique is applied to a wide-band differential common gate (CG) LNA employing noise cancelation method. Post-layout simulations exhibit that the proposed technique increases IIP3 and P1dB considerably to +11.9 and +1 dBm, respectively at 1.8 GHz. The LNA achieves voltage gain of 13.7–13.9 dB, noise figure of 3–3.28 dB, and S11 less than −10 dB, while consuming only 16.5 mW. The layout schematic occupies 0.515 × 0.220 mm2 of chip area.