A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM

Abstract

A quad-band GSM/GPRS/EDGE cellular system, implemented in 65-nm CMOS, is integrated in a multimedia SoC with BT and FM. A low-IF receiver with digital IRR tracking is selected for its smaller area and better noise figure. The receiver achieves a sensitivity of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 110 dBm, an IIP3 of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 9.5 dBm, and a calibrated image rejection ratio of 65 dBc, while consuming 61 mA. The polar transmitter architecture is chosen for its SAW-less TX capability, smaller area, and low current consumption. It achieves an ORFS (output radio frequency spectrum) of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-$</tex></formula> 68 dB and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-$</tex></formula> 64 dB at 400 kHz in GMSK and EDGE mode, respectively, while consuming 61 mA. The loop gain normalization, dc offset and AM/PM delay of the polar system are compensated to be better than 1% error, 1 mV, and 1.9 ns within 170 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu$</tex></formula> s, respectively. Several techniques are employed to minimize interference coupling within the SoC; these include frequency planning, circuit implementation, transceiver architecture optimization, and digital clock selection. The measured sensitivity and the output spectrum of the three wireless systems under full-feature phone operation are virtually unchanged.