A 6 pJ/bit transmitter front end in 130 nm CMOS technology for wireless interconnect

Abstract

A wireless interconnect system offers solutions to the routing complexity and latency bottlenecks of the wired interconnect for multicore processors. In this paper, a simple transmitter front-end is developed as a component of a wireless interconnect system. Silicon cost and power consumption are primary design constraints. Direct up-conversion architecture is adopted for low power consumption by limiting the number of stages in the system. On-off keying modulation is employed to modulate the carrier with baseband binary data. The system consists of a voltage controlled oscillator (VCO) and an on-off keying (OOK) Modulator. The designs achieve a 6 pJ/bit energy consumption and are implemented in 130nm CMOS Technology. The VCO consumes a power of 8.4 mW running at 11.3 GHz and the OOK modulator consumes 3.6 mW while transmitting a binary 1 at a single VDD. A data rate of 2 Gbps is achieved.