Abstract
A twisted-pair quadrature amplitude modulation (QAM) transceiver IC accommodates data rates from 0 to 52 Mb/s. The QAM transceiver is a monolithic mixed signal device implemented in 0.35 /spl mu/m four-level metal single-poly CMOS. The transceiver supports 4-, 16-, 32-, 64-, 128-, and 256-QAM modulation formats and operates at symbol rates as high as 13 MBaud. The transceiver chip contains a fully-integrated transmitter, including ATM UTOPIA or synchronous input interface, packet-formatting logic, Reed-Solomon forward error correction (FEC) encoding, a rate-adaptive QAM modulator and a 10 b D/A converter. The receiver portion of the transceiver chip consists of a high-precision 10 b A/D converter, a programmable rate QAM demodulator, all-digital clock and carrier recovery loops, powerful adaptive filters to provide rejection of narrowband interferers and the equalization of severe channel distortions, FEC decoding, ATM UTOPIA or synchronous output interface and an analog phase-lock loop for internal clock generation from a single crystal reference. The QAM transceiver may be used in applications such as asymmetric digital subscriber line (ADSL) and very high-speed digital subscriber line (VDSL) services.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
