A 50 Gb/s clock and data recovery circuit in 45 nm CMOS SOI, SPCLO GF process, for high-speed communication on fiber optics in data centers

Clock and data recovery (CDR) circuit plays a vital role for wired serial link communication in multi mode based system on chip (SOC). In wire linked communication systems, when data flows without any accompanying clock over a single wire, the receiver of the system is required to recover this data synchronously without losing the information. Therefore there exists a need for CDR circuits in the receiver of the system for recovering the clock or timing information from these data. The existing Octa-rate CDR circuit is not compatible to real time data, such a data is unpredictable, non periodic and has different arrival times and phase widths. Thus the proposed PRN based Octa-rate Clock and Data Recovery circuit is made compatible to real time data by introducing a Random Sequence Generator. The proposed PRN based Octa-rate Clock and Data Recovery circuit consists of PRN Sequence Generator, 16-Phase Generator, Early Late Phase Detector and Delay Line Controller. The FSM based Delay Line Controller controls the delay length and introduces the required delay in the input data. The PRN based Octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. The delay between the input and the generation of output is measured and analyzed using Logic Analyzer AGILENT 1962 A.

Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction.

This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.

In this paper, a 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data rate changes. The CDR circuit is implemented with TSMC 0.18-um 1P6M CMOS technology. The simulation results show the proposed CDR circuit recovers the incoming data.

Clock and data recovery (CDR) circuit is a key component used in Ethernet, optical network and serial link. High-speed and low-power CDR circuits find their applications in a variety of communication systems. The thesis introduces the architectures and some design issues of clock and data recovery circuits. A low voltage and high speed CDR is then designed and implemented. Behavior model built by using Matlab Simulink is used to simulate and analyze the function and stability of the CDR. A 1.2V 2.5Gbps CDR circuit has been implemented in TSMC 0.18um 1P6M CMOS process. A half-rate CDR circuit using 1.25GHz VCO is presented. The VCO uses a modified delay cell to extend the linear control range to 0~1.2V for low voltage operation. The linearity and gain of the VCO transfer characteristics are much improved. The modified VCO works at a tuning range from 0.76 GHz to 1.5GHz, and its peak-to-peak jitter at 1.25 GHz is 30ps. The phase noise is -100.7dBc /Hz at 1MHz offset from a 1.25GHz center frequency. The power consumption of the core circuit is 1.8mW, with buffer is 3.21mW. The clock and data recovery circuit consumed 49.5mW at 1.2V power supply, and its jitter is 175ps. The power consumption of the half-rate phase detector is 12.7 mW. The circuit buffers consumed 33mW. For testing purpose a 2.5GHz PLL and a 215-1 PRBS generator are included in the chip. The whole chip area is 920um*920um. The CDR circuit area is 322.4um*403.3um.

A 10Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10Gb/s quarter-rate CDR circuit has been fabricated in a 0.13um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22ps and 30.7ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2mm2. This CDR circuit consumes 122.5mW excluding output buffers from a supply voltage of 1.5V.

In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-/spl mu/m CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data.

A 10 Gb/s clock and data recovery (CDR) circuits which extract the clock signal from non-return-zero (NRZ) random data stream are very important to the 10-gigabit -per-second integrated receivers. The half-rate linear phase detector for 10-Gb/s clock and data recovery (CDR) circuit is designed to 0.18-um standard CMOS technology. This half-rate phase detector is composed of four latches and two exclusive OR (XOR) gates. The proposed circuits of phase detector provide a linear characteristic and it has a configuration of MOS current-mode logic (MCML) gates

A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 /spl mu/m CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted frequency acquisition range and a fast frequency acquisition time. The CDR is implemented in a 180 nm CMOS process, consumes 62 mW of power including I/O buffers at 2.7 Gb/s with a 1.8 V supply. The CDR takes 15.2 μs of a maximum locking time when the data rate locked at 2.7 Gb/s is switched to 320 Mb/s. The CDR circuit has shown 59 ps and 75.4 ps peak-to-peak jitter in recovered clock and data, respectively, with 2.7 Gb/s input data.

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.

We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be programmed by scanning the dead-zone width of a variable dead-zone BBPD in the time domain. Its linear-like gain characteristics result in less sensitive CDR performance against input jitter and process, voltage, and temperature (PVT) variations. In addition, a built-in on-chip jitter monitor can be easily implemented using our ML-BBPD. A prototype 1.25-Gb/s CDR based on our ML-BBPD with a built-in jitter monitor is realized with 0.18- $\mu{\rm m}$ CMOS technology and its performance is successfully verified with measurement.

This paper presents a clock and data recovery (CDR) circuit with a new half-rate phase detector. The half-rate CDR circuit senses the input random data at full rate but employs a VCO running at a half frequency of the input data. At the locked condition, the circuit will generate two 625-Mb/s output sequences. The new half-rate phase detector applicable to the 1.25-Gb/s NRZ data stream is adopted to reduce the dead zone in phase characteristic. The CDR circuit is fabricated using the 0.35/spl mu/m CMOS technology and occupies 1800/spl mu/m/spl times/1800/spl mu/m chip area. Total power consumption of the chip is 54.8 mW under a 3-V supply voltage.

The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm² and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.

We present a 40-Gbit/s-class clock and data recovery (CDR) circuit with a new lock detector. The lock detector operates robustly with a linear-type phase detector. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40, 43, and 45-Gbit/s PRBS with a length of 2/sup 31/-1. By attaching a frequency search and phase control (FSPC) circuit to the chip, the CDR circuit pulls in throughout a 39-45 Gbit/s range. The fabricated IC dissipates 1.89 W at a supply voltage of -4.5V.