A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2<formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula>-oversampling phase-tracking CDR, implemented in 90<formula formulatype="inline"><tex Notation="TeX">$\,$</tex></formula>nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of <formula formulatype="inline"> <tex Notation="TeX">${\pm }{\hbox{615~ppm}}$</tex></formula> between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate <formula formulatype="inline"><tex Notation="TeX">${≪} \hbox{10}^{-12}$</tex></formula> was verified up to 38 Gb/s using a 2<formula formulatype="inline"><tex Notation="TeX">$ ^{7} -$</tex></formula>1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90<formula formulatype="inline"><tex Notation="TeX">$~$</tex></formula>nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 <formula formulatype="inline"><tex Notation="TeX">${\hbox{mm}}^{2}$</tex> </formula>. </para>