A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations

Abstract

In the current context of strict low-power requirements, complex dynamic frequency and voltage scale systems try to constantly push the operating conditions of electronic chips to the lower bound that fulfills the performance requirements. Also, at test time of a synchronous electronic system, any occurrence of timing violations, especially hold time violations, must be identified, located and corrected. Critical path monitors serve these two purposes, they measure the delays where transients are produced in relation to the clock signal for the critical paths of the system. This work introduces a critical path monitor architecture that yields two configurable digital outputs: one for setup time violations, and another for hold time violations. The monitor directly senses the critical path, without the need to introduce synthesized replicas. The architecture has been validated in a 40nm commercial technology, it takes an area of 4028 $\mu \mathrm{m}^{2}$ and it is very robust against PVT variations.