A 3D -SVPWM Algorithm Design and its FPGA IP – Core Implementation for MLIs Operating Over a Wide Modulation Range

Abstract

This work reports a simplified approach to implement three dimensional space vector pulse width modulation (3D-SVM) for multilevel inverter (MLI). The 3-D SVM is advanced method of 2-D SVM, and it inherits all the advantages of traditional 2-D. A simple technique for the selection of switching states to find the reference vector without redundant switching vectors is proposed here. This paper treasures the reference vector by categorizing sub cubes and tetrahedrons by using mathematical environments and Calculates the on-state durations of the respective switching state vectors without involving trigonometric functions or look up tables and angle determination. The Detailed analysis, verification by computer simulation using MATLAB –Simulink platform. The proposed algorithm is more suitable to the hardware implementation by significantly reducing the hardware core components and cost. Based on the simplified 3D-SVM, the reduced memory intellectual property (IP) core has been developed using Verilog hardware description language (VHDL).The designed 3D-SVM IP core is validation through FPGA-SPARTAN III- XC3SD1800A board and tested with prototype 3-phase 3-level Neutral Point Clamped -MLI. Here the cost of the proposed technique is independent of voltage levels of inverter; this algorithm can minimize extremely the time and complexity of calculation, since the proposed 3D-SVM IP core is simpler and faster