Abstract

This paper presents a 13-b, 2.56-μs conversion time, 2 V input range, 32-channel single slope analog-to-digital converter (ADC) called OWB-1 and implemented in a 0.35-μm CMOS commercial technology. It is based on an improved Wilkinson architecture. An interpolator composed by a delay lock loop is used to increase the time resolution of the counter by a factor of 32, while keeping a low power consumption and ensuring the high dynamic performance of the ADC. Measurements performed on the ADC have shown that the noise is better than 0.86 LSB over the full conversion range, its differential nonlinearity is in the range of -0.28/+0.31 LSB and its integral nonlinearity is within -1.3/+2.1 LSB. The total power consumption of the chip is 57 mW for 32 active channels. A new temperature compensation system based on a servo loop has also been integrated into the chip to compensate for temperature effects in the -40°C to +40°C range. Special design techniques have been used to make the ASIC immune to single event latchup. OWB-1 readout is optimized for a new low power microgamma camera (Caliste-MC2) with digital output based on a 32 x 32 CdTe or CdZnTe pixel matrix.

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