A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

Abstract

A 25-Gb/s low-power Clock and Data Recovery (CDR) with Clocked CMOS (C2MOS) D-Flip-Flop (D-FF) for low power operation is presented. In a CDR circuit, D-FF is one of the dominant factor on the power consumption. In this work, we design the low-power CDR with 25-GHz clock by using a C2MOS D-FF. C2MOS D-FF reduces the power by 84 % compared with a conventional current mode logic (CML) D-FF. To validate the proposed design, we fabricated 25-Gb/s CDR in a 65-nm CMOS process. The area for the core circuits is 0.047 mm2, and the power consumption without output buffers is 13 mW, which is 13 % of that for the conventional 65-nm CDR with 25-GHz clock.