Abstract
Recently, several delay-locked loop (DLL) circuits for on-chip clock supply have been reported. In this paper a new 2-loop circuit has been designed for on-chip clock-supply applications which require a quick pull-in, suppressed jitter in a wide operating frequency range. The design technologies included are: 1) A 2-loop architecture in which a frequency-locked loop (FLL) is provided separately from a DLL for quick pull-in over a wide frequency range; 2) A current-mode phase detector (CMPD) used in the DLL, which makes use of a flip-flop metastability for increasing the phase-difference detecting sensitivity.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
