Abstract
This paper provides a low power low noise differential amplifier designed for Wireless Sensor Network (WSN) in TSMC 0.18 µm RF CMOS process. It should work well centered at 2.44 GHz frequency and the forward gain is variable with highest gain at 12 dB to lowest gain at −2 dB by 2 dB steps. In this paper, a two-stage cascade common-gate (CG) topology and two external inductor choke coils are used to achieve input matching of LNA under low power consumption, and a differential inductor has been designed as the load to achieve reasonable gain and reduce chip area simultaneously. It has been simulated and verified by means of Cadence Spectre. The NF (Noise Figure) at high gain (12.5 dB) is 3.9 dB, the input referenced 1dB compression point (IP1dB) is about −1 dBm at lowest gain mode. The LNA consumes about 1.5 mA current from 1.8 V power supply.
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