Abstract

A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100 Hz and 10 kHz, respectively. The maximum supply current is 240 nA. The chip area is 0.016 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.