Abstract
We introduce the first monolithic step-up dc–dc converter operating at deep sub-1 V (i.e., 0.18–0.4 V) that outputs significant power for Internet-of-Things with a peak power efficiency of 81.2% at 50 $ {\mu }\text{W}$ output power for the 0.18-V input and 87.1% at 300 $ {\mu }\text{W}$ output power for 0.4 V. It is implemented in 16-nm FinFET CMOS and uses an MOS transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter verifies the dc–dc output quality.
Highlights
The rapid CMOS technology progress has been a boon to the emerging applications of Internet-of-Things (IoT) [1], [2]
To bridge the gap of voltage difference, while avoiding bulky inductors, we explore a switched-capacitor (SC) voltage doubler [see Fig. 1] that can handle supply inputs down to 0.18 V with high (>80%) efficiency and demonstrate it with a sensitive circuitry of time-to-digital converter (TDC) that requires fine resolution
Recent work [3]–[7] in SC dc–dc converters has focused on enhancing the conversion efficiency by increasing capacitance density of a pumping or flying capacitor (CFLY) while keeping its bottom plate (BP) parasitic capacitance (CPAR) at a minimum
Summary
The rapid CMOS technology progress has been a boon to the emerging applications of Internet-of-Things (IoT) [1], [2]. Recent work [3]–[7] in SC dc–dc converters has focused on enhancing the conversion efficiency by increasing capacitance density of a pumping or flying capacitor (CFLY) while keeping its bottom plate (BP) parasitic capacitance (CPAR) at a minimum. They all operate at higher than 1 V. In [3], stage-outphasing and multiphase softcharging techniques are presented where soft-charging of the flying capacitors leads to improved capacitance utilization and higher efficiency and power density These techniques are beneficial for higher voltage conversion ratios and do not lead to performance improvement of a doubler. This is especially advantageous in an ultralow voltage (ULV) design, since traditionally, the ratio of the parasitic to the main gate-oxide capacitance increases as the voltage decreases
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