A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications

Abstract

This paper describes the design of a low-voltage phase-locked loop (PLL) in a dual frequency synthesizer IC. The dual frequency synthesizes IC integrates a 1.1 GHz RF PLL, a 300 MHz IF PLL, a circuit for the Colpitt's oscillator, and two 8-bit DACs. The RF PLL, with an external VCO and loop filter, exhibits close-in phase noise of -72 dBc/Hz at 150 Hz away from the carrier and spurious suppression of better than -65 dBc over a wide charge pump tuning range of 0.2 V to Vdd-0.4 V. The whole chip consumes 3.5 mA at 1.8 V power supply. This chip was fabricated in a 0.35 /spl mu/m digital CMOS process with typical V/sub tn/ and V/sub tp/ of 0.6 V and 0.8 V respectively.