Abstract
This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 μm CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems I: Regular Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
