Abstract
This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of −95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a $0.18~\mu \text{m}$ CMOS triple-well process and has a total power consumption of $54~\mu \text{W}$ . Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of $5.23~\mu \text{V}_{\text {rms}}$ , power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 $\text{M}\Omega $ .
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