Abstract
The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wide-band PLL topology with a high. reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump, circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
